Coerce lowering for the C ABI updated. Updated aarch64 fixes.

test/test_suite/struct/struct_as_value_aarch64.c3t

@@ -0,0 +1,45 @@
+// #target: aarch64_linux
+module test;
+
+struct Event
+{
+    int op;
+}
+
+func Event test(int x)
+{
+  Event foo = { 1 };
+  Event bar = { 2 };
+  return x ? foo : bar;
+}
+
+// #expect: test.ll
+
+  %x = alloca i32, align 4
+  %foo = alloca %Event, align 4
+  %bar = alloca %Event, align 4
+  %tempaddr = alloca %Event, align 4
+  store i32 %0, i32* %x, align 4
+  %1 = bitcast %Event* %foo to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 bitcast (%Event* @.__const to i8*), i32 4, i1 false)
+  %2 = bitcast %Event* %bar to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %2, i8* align 4 bitcast (%Event* @.__const.1 to i8*), i32 4, i1 false)
+  %3 = load i32, i32* %x, align 4
+  %intbool = icmp ne i32 %3, 0
+  br i1 %intbool, label %cond.lhs, label %cond.rhs
+
+cond.lhs:
+  %4 = load %Event, %Event* %foo, align 4
+  br label %cond.phi
+
+cond.rhs:
+  %5 = load %Event, %Event* %bar, align 4
+  br label %cond.phi
+
+cond.phi:
+  %val = phi %Event [ %4, %cond.lhs ], [ %5, %cond.rhs ]
+  store %Event %val, %Event* %tempaddr, align 4
+  %dive = getelementptr inbounds %Event, %Event* %tempaddr, i32 0, i32 0
+  %6 = load i32, i32* %dive, align 4
+  %7 = zext i32 %6 to i64
+  ret i64 %7