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https://github.com/c3lang/c3c.git
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Fixes to asm. Added additional x86 instructions.
This commit is contained in:
Christoffer Lerno
committed by
Christoffer Lerno
Christoffer Lerno
parent
ba9b203c52
commit
d4aec525f5
@@ -35,38 +35,6 @@ typedef enum
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X86_XMM13,
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X86_XMM14,
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X86_XMM15,
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X86_YMM0,
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X86_YMM1,
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X86_YMM2,
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X86_YMM3,
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X86_YMM4,
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X86_YMM5,
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X86_YMM6,
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X86_YMM7,
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X86_YMM8,
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X86_YMM9,
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X86_YMM10,
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X86_YMM11,
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X86_YMM12,
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X86_YMM13,
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X86_YMM14,
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X86_YMM15,
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X86_ZMM0,
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X86_ZMM1,
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X86_ZMM2,
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X86_ZMM3,
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X86_ZMM4,
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X86_ZMM5,
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X86_ZMM6,
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X86_ZMM7,
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X86_ZMM8,
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X86_ZMM9,
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X86_ZMM10,
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X86_ZMM11,
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X86_ZMM12,
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X86_ZMM13,
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X86_ZMM14,
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X86_ZMM15,
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X86_K0,
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X86_K1,
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X86_K2,
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@@ -136,38 +104,6 @@ static const char *X86ClobberNames[] = {
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[X86_XMM13] = "xmm13",
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[X86_XMM14] = "xmm14",
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[X86_XMM15] = "xmm15",
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[X86_YMM0] = "ymm0",
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[X86_YMM1] = "ymm1",
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[X86_YMM2] = "ymm2",
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[X86_YMM3] = "ymm3",
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[X86_YMM4] = "ymm4",
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[X86_YMM5] = "ymm5",
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[X86_YMM6] = "ymm6",
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[X86_YMM7] = "ymm7",
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[X86_YMM8] = "ymm8",
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[X86_YMM9] = "ymm9",
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[X86_YMM10] = "ymm10",
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[X86_YMM11] = "ymm11",
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[X86_YMM12] = "ymm12",
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[X86_YMM13] = "ymm13",
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[X86_YMM14] = "ymm14",
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[X86_YMM15] = "ymm15",
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[X86_ZMM0] = "zmm0",
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[X86_ZMM1] = "zmm1",
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[X86_ZMM2] = "zmm2",
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[X86_ZMM3] = "zmm3",
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[X86_ZMM4] = "zmm4",
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[X86_ZMM5] = "zmm5",
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[X86_ZMM6] = "zmm6",
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[X86_ZMM7] = "zmm7",
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[X86_ZMM8] = "zmm8",
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[X86_ZMM9] = "zmm9",
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[X86_ZMM10] = "zmm10",
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[X86_ZMM11] = "zmm11",
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[X86_ZMM12] = "zmm12",
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[X86_ZMM13] = "zmm13",
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[X86_ZMM14] = "zmm14",
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[X86_ZMM15] = "zmm15",
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[X86_K0] = "k0",
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[X86_K1] = "k1",
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[X86_K2] = "k2",
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@@ -224,3 +160,5 @@ static const char *x86_xmm_regs[] = { "$xmm0", "$xmm1", "$xmm2", "$xmm3", "$xmm4
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static const char *x86_ymm_regs[] = { "$ymm0", "$ymm1", "$ymm2", "$ymm3", "$ymm4", "$ymm5", "$ymm6", "$ymm7",
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"$ymm8", "$ymm9", "$ymm10", "$ymm11", "$ymm12", "$ymm13", "$ymm14", "$ymm15" };
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static const char *x86_zmm_regs[] = { "$zmm0", "$zmm1", "$zmm2", "$zmm3", "$zmm4", "$zmm5", "$zmm6", "$zmm7",
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"$zmm8", "$zmm9", "$zmm10", "$zmm11", "$zmm12", "$zmm13", "$zmm14", "$zmm15" };
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@@ -58,9 +58,19 @@ INLINE AsmArgBits parse_bits(const char **desc)
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}
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if (memcmp("128", *desc, 3) == 0)
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{
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*desc += 2;
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*desc += 3;
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return ARG_BITS_128;
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}
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if (memcmp("256", *desc, 3) == 0)
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{
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*desc += 3;
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return ARG_BITS_256;
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}
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if (memcmp("512", *desc, 3) == 0)
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{
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*desc += 3;
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return ARG_BITS_512;
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}
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error_exit("Invalid bits: %s.", *desc);
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}
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@@ -95,7 +105,10 @@ INLINE AsmArgType decode_arg_type(const char **desc)
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*desc += 2;
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goto NEXT;
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}
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error_exit("Unexpected string %s", &desc[-1]);
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error_exit("Unexpected string %s", &(*desc)[-1]);
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case 'v':
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arg_type.vec_bits |= parse_bits(desc);
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goto NEXT;
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case 'i':
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if (memcmp("mm", *desc, 2) == 0)
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{
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@@ -119,7 +132,7 @@ INLINE AsmArgType decode_arg_type(const char **desc)
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goto NEXT;
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}
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default:
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error_exit("Unexpected string '%s'.", &desc[-1]);
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error_exit("Unexpected string '%s'.", &(*desc)[-1]);
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}
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NEXT:
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switch (**desc)
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@@ -236,22 +249,22 @@ static void init_asm_aarch64(void)
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reg_instr("strh", "r32/r64, w:mem");
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reg_instr("stp", "r32/r64, r32/r64, w:mem");
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reg_instr("mov", "w:r32/r64, mem");
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reg_register_list(aarch64_quad_regs, 32, ASM_REG_INT, 64, AARCH64_R0);
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reg_register_list(aarch64_long_regs, 32, ASM_REG_INT, 32, AARCH64_R0);
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reg_register_list(aarch64_f128_regs, 32, ASM_REG_FLOAT, 128, AARCH64_Q0);
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reg_register_list(aarch64_double_regs, 32, ASM_REG_FLOAT, 64, AARCH64_Q0);
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reg_register_list(aarch64_float_regs, 32, ASM_REG_FLOAT, 32, AARCH64_Q0);
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reg_register_list(aarch64_f16_regs, 32, ASM_REG_FLOAT, 16, AARCH64_Q0);
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reg_register_list(aarch64_f8_regs, 32, ASM_REG_FLOAT, 8, AARCH64_Q0);
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reg_register_list(aarch64_v8b_regs, 32, ASM_REG_IVEC, 64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v16b_regs, 32, ASM_REG_IVEC, 128,AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v4h_regs, 32, ASM_REG_IVEC, 64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v8h_regs, 32, ASM_REG_IVEC, 128, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v2s_regs, 32, ASM_REG_IVEC, 64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v4s_regs, 32, ASM_REG_IVEC, 128, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v1d_regs, 32, ASM_REG_IVEC, 64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v2d_regs, 32, ASM_REG_IVEC, 128, AARCH64_FIRST_RV_CLOBBER);
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reg_register("$sp", ASM_REG_INT, 64, AARCH64_R31);
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reg_register_list(aarch64_quad_regs, 32, ASM_REG_INT, ARG_BITS_64, AARCH64_R0);
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reg_register_list(aarch64_long_regs, 32, ASM_REG_INT, ARG_BITS_32, AARCH64_R0);
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reg_register_list(aarch64_f128_regs, 32, ASM_REG_FLOAT, ARG_BITS_128, AARCH64_Q0);
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reg_register_list(aarch64_double_regs, 32, ASM_REG_FLOAT, ARG_BITS_64, AARCH64_Q0);
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reg_register_list(aarch64_float_regs, 32, ASM_REG_FLOAT, ARG_BITS_32, AARCH64_Q0);
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reg_register_list(aarch64_f16_regs, 32, ASM_REG_FLOAT, ARG_BITS_16, AARCH64_Q0);
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reg_register_list(aarch64_f8_regs, 32, ASM_REG_FLOAT, ARG_BITS_8, AARCH64_Q0);
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reg_register_list(aarch64_v8b_regs, 32, ASM_REG_IVEC, ARG_BITS_64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v16b_regs, 32, ASM_REG_IVEC, ARG_BITS_128, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v4h_regs, 32, ASM_REG_IVEC, ARG_BITS_64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v8h_regs, 32, ASM_REG_IVEC, ARG_BITS_128, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v2s_regs, 32, ASM_REG_IVEC, ARG_BITS_64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v4s_regs, 32, ASM_REG_IVEC, ARG_BITS_128, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v1d_regs, 32, ASM_REG_IVEC, ARG_BITS_64, AARCH64_FIRST_RV_CLOBBER);
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reg_register_list(aarch64_v2d_regs, 32, ASM_REG_IVEC, ARG_BITS_128, AARCH64_FIRST_RV_CLOBBER);
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reg_register("$sp", ASM_REG_INT, ARG_BITS_64, AARCH64_R31);
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}
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static void init_asm_wasm(void)
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@@ -294,11 +307,24 @@ static void init_asm_x86(void)
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reg_instr_clob("adcw", cc_flag_mask, "rw:r16/mem, r16/mem/imm16/immi8");
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reg_instr_clob("adcl", cc_flag_mask, "rw:r32/mem, r32/mem/imm32/immi8");
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reg_instr_clob("adcq", cc_flag_mask, "rw:r64/mem, r64/mem/immi32/immi8");
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reg_instr_clob("adcxl", cc_flag_mask, "r32, rw:r32/mem");
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reg_instr_clob("adcxq", cc_flag_mask, "r64, rw:r64/mem");
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reg_instr_clob("addb", cc_flag_mask, "rw:r8/mem, r8/mem/imm8");
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reg_instr_clob("addw", cc_flag_mask, "rw:r16/mem, r16/mem/imm16/immi8");
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reg_instr_clob("addl", cc_flag_mask, "rw:r32/mem, r32/mem/imm32/immi8");
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reg_instr_clob("addq", cc_flag_mask, "rw:r64/mem, r64/mem/immi32/immi8");
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reg_instr("addpd", "rw:v128, v128/mem");
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reg_instr("addps", "rw:v128, v128/mem");
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reg_instr("addsd", "rw:v128, v128/mem");
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reg_instr("addss", "rw:v128, v128/mem");
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reg_instr("vaddpd", "w:v128/v256/v512, v128/v256/v512, v128/v256/v512/mem");
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reg_instr("vaddps", "w:v128/v256/v512, v128/v256/v512, v128/v256/v512/mem");
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reg_instr("vaddsd", "w:v128, v128, v128/mem");
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reg_instr("vaddss", "w:v128, v128, v128/mem");
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reg_instr_clob("cbtw", rax_mask, NULL);
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reg_instr_clob("cwtl", rax_mask, NULL);
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reg_instr_clob("cltq", rax_mask, NULL);
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@@ -380,21 +406,22 @@ static void init_asm_x86(void)
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asm_target.extra_clobbers = "~{flags},~{dirflag},~{fspr}";
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if (platform_target.arch == ARCH_TYPE_X86)
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{
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reg_register_list(x86_long_regs, 8, ASM_REG_INT, 32, X86_RAX);
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reg_register_list(x86_word_regs, 8, ASM_REG_INT, 16, X86_RAX);
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reg_register_list(x86_low_byte_regs, 8, ASM_REG_INT, 8, X86_RAX);
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reg_register_list(x86_float_regs, 8, ASM_REG_FLOAT, 80, X86_ST0);
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reg_register_list(x86_xmm_regs, 8, ASM_REF_MMX, 128, X86_MM0);
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reg_register_list(x86_long_regs, 8, ASM_REG_INT, ARG_BITS_32, X86_RAX);
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reg_register_list(x86_word_regs, 8, ASM_REG_INT, ARG_BITS_16, X86_RAX);
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reg_register_list(x86_low_byte_regs, 8, ASM_REG_INT, ARG_BITS_8, X86_RAX);
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reg_register_list(x86_float_regs, 8, ASM_REG_FLOAT, ARG_BITS_80, X86_ST0);
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reg_register_list(x86_xmm_regs, 8, ASM_REF_FVEC, ARG_BITS_128, X86_MM0);
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}
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else
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{
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reg_register_list(x64_quad_regs, 15, ASM_REG_INT, 64, X86_RAX);
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reg_register_list(x86_long_regs, 15, ASM_REG_INT, 32, X86_RAX);
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reg_register_list(x86_word_regs, 15, ASM_REG_INT, 16, X86_RAX);
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reg_register_list(x86_low_byte_regs, 15, ASM_REG_INT, 8, X86_RAX);
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reg_register_list(x86_high_byte_regs, 4, ASM_REG_INT, 8, X86_RAX);
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reg_register_list(x86_xmm_regs, 16, ASM_REF_MMX, 128, X86_XMM0);
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reg_register_list(x86_ymm_regs, 16, ASM_REF_MMX, 128, X86_YMM0);
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reg_register_list(x64_quad_regs, 15, ASM_REG_INT, ARG_BITS_64, X86_RAX);
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reg_register_list(x86_long_regs, 15, ASM_REG_INT, ARG_BITS_32, X86_RAX);
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reg_register_list(x86_word_regs, 15, ASM_REG_INT, ARG_BITS_16, X86_RAX);
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reg_register_list(x86_low_byte_regs, 15, ASM_REG_INT, ARG_BITS_8, X86_RAX);
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reg_register_list(x86_high_byte_regs, 4, ASM_REG_INT, ARG_BITS_8, X86_RAX);
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reg_register_list(x86_xmm_regs, 16, ASM_REF_FVEC, ARG_BITS_128, X86_XMM0);
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reg_register_list(x86_ymm_regs, 16, ASM_REF_FVEC, ARG_BITS_256, X86_XMM0);
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reg_register_list(x86_zmm_regs, 16, ASM_REF_FVEC, ARG_BITS_512, X86_XMM0);
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}
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}
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void init_asm(void)
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@@ -126,14 +126,10 @@ static inline char *codegen_create_x86_att_asm(AsmInlineBlock *block)
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Expr** args = ast->asm_stmt.args;
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unsigned arg_count = vec_size(args);
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scratch_buffer_append_char(' ');
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if (arg_count > 1)
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for (unsigned i = arg_count; i > 0; i--)
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{
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codegen_create_x86att_arg(block, input_arg_offset, args[1]);
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scratch_buffer_append(", ");
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}
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if (arg_count)
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{
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codegen_create_x86att_arg(block, input_arg_offset, args[0]);
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if (i != arg_count) scratch_buffer_append(", ");
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codegen_create_x86att_arg(block, input_arg_offset, args[i - 1]);
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}
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scratch_buffer_append_char('\n');
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}
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@@ -133,10 +133,11 @@ typedef struct
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bool is_write : 1;
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bool is_readwrite : 1;
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bool is_address : 1;
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AsmArgBits imm_arg_ubits : 8;
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AsmArgBits imm_arg_ibits : 8;
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AsmArgBits ireg_bits : 8;
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AsmArgBits float_bits : 8;
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AsmArgBits imm_arg_ubits : 16;
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AsmArgBits imm_arg_ibits : 16;
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AsmArgBits ireg_bits : 16;
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AsmArgBits float_bits : 16;
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AsmArgBits vec_bits : 16;
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} AsmArgType;
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typedef struct
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@@ -273,8 +273,6 @@ typedef enum
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ASM_REG_FLOAT,
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ASM_REG_IVEC,
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ASM_REF_FVEC,
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ASM_REF_SSE,
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ASM_REF_MMX,
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} AsmRegisterType;
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typedef enum
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@@ -284,7 +282,9 @@ typedef enum
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ARG_BITS_32 = 1 << 2,
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ARG_BITS_64 = 1 << 3,
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ARG_BITS_128 = 1 << 4,
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ARG_BITS_80 = 1 << 5,
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ARG_BITS_256 = 1 << 5,
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ARG_BITS_512 = 1 << 6,
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ARG_BITS_80 = 1 << 7,
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} AsmArgBits;
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typedef enum
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@@ -64,11 +64,9 @@ INLINE bool sema_reg_is_valid_in_slot(AsmRegister *reg, AsmArgType arg_type)
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return (arg_type.ireg_bits & reg->bits) != 0;
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case ASM_REG_FLOAT:
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return (arg_type.float_bits & reg->bits) != 0;
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case ASM_REG_IVEC:
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case ASM_REF_FVEC:
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case ASM_REF_SSE:
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case ASM_REF_MMX:
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TODO
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case ASM_REG_IVEC:
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return (arg_type.vec_bits & reg->bits) != 0;
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}
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UNREACHABLE
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}
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@@ -190,7 +188,7 @@ static inline bool sema_check_asm_arg_reg(SemaContext *context, AsmInlineBlock *
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SEMA_ERROR(expr, "Expected a valid register name.");
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return false;
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}
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if (sema_reg_is_valid_in_slot(reg, arg_type))
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if (!sema_reg_is_valid_in_slot(reg, arg_type))
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{
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SEMA_ERROR(expr, "'%s' is not valid in this slot.", reg->name);
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return false;
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@@ -1 +1 @@
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#define COMPILER_VERSION "0.3.42"
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#define COMPILER_VERSION "0.3.43"
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30
test/test_suite/asm/asm_ops_x64_2.c3t
Normal file
30
test/test_suite/asm/asm_ops_x64_2.c3t
Normal file
@@ -0,0 +1,30 @@
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// #target: macos-x64
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module test;
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fn void main(char[][] args)
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{
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int foo;
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asm
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{
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adcxl $eax, $ecx;
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adcxq $rax, $rcx;
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addpd $xmm1, $xmm2;
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addps $xmm1, $xmm2;
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addsd $xmm1, $xmm2;
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addss $xmm1, $xmm2;
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vaddpd $xmm1, $xmm2, $xmm3;
|
||||
vaddpd $ymm1, $ymm2, $ymm3;
|
||||
vaddpd $xmm1, $xmm2, [&foo];
|
||||
vaddps $xmm1, $xmm2, $xmm3;
|
||||
vaddps $ymm1, $ymm2, $ymm3;
|
||||
vaddps $xmm1, $xmm2, [&foo];
|
||||
vaddsd $xmm1, $xmm2, $xmm3;
|
||||
vaddsd $xmm1, $xmm2, [&foo];
|
||||
vaddss $xmm1, $xmm2, $xmm3;
|
||||
vaddss $xmm1, $xmm2, [&foo];
|
||||
}
|
||||
}
|
||||
|
||||
/* #expect: test.ll
|
||||
|
||||
"adcxl %ecx, %eax\0Aadcxq %rcx, %rax\0Aaddpd %xmm2, %xmm1\0Aaddps %xmm2, %xmm1\0Aaddsd %xmm2, %xmm1\0Aaddss %xmm2, %xmm1\0Avaddpd %xmm3, %xmm2, %xmm1\0Avaddpd %ymm3, %ymm2, %ymm1\0Avaddpd $0, %xmm2, %xmm1\0Avaddps %xmm3, %xmm2, %xmm1\0Avaddps %ymm3, %ymm2, %ymm1\0Avaddps $0, %xmm2, %xmm1\0Avaddsd %xmm3, %xmm2, %xmm1\0Avaddsd $0, %xmm2, %xmm1\0Avaddss %xmm3, %xmm2, %xmm1\0Avaddss $0, %xmm2, %xmm1\0A", "*m,~{cc},~{rcx},~{xmm1},~{flags},~{dirflag},~{fspr}"
|
||||
30
test/test_suite2/asm/asm_ops_x64_2.c3t
Normal file
30
test/test_suite2/asm/asm_ops_x64_2.c3t
Normal file
@@ -0,0 +1,30 @@
|
||||
// #target: macos-x64
|
||||
module test;
|
||||
|
||||
fn void main(char[][] args)
|
||||
{
|
||||
int foo;
|
||||
asm
|
||||
{
|
||||
adcxl $eax, $ecx;
|
||||
adcxq $rax, $rcx;
|
||||
addpd $xmm1, $xmm2;
|
||||
addps $xmm1, $xmm2;
|
||||
addsd $xmm1, $xmm2;
|
||||
addss $xmm1, $xmm2;
|
||||
vaddpd $xmm1, $xmm2, $xmm3;
|
||||
vaddpd $ymm1, $ymm2, $ymm3;
|
||||
vaddpd $xmm1, $xmm2, [&foo];
|
||||
vaddps $xmm1, $xmm2, $xmm3;
|
||||
vaddps $ymm1, $ymm2, $ymm3;
|
||||
vaddps $xmm1, $xmm2, [&foo];
|
||||
vaddsd $xmm1, $xmm2, $xmm3;
|
||||
vaddsd $xmm1, $xmm2, [&foo];
|
||||
vaddss $xmm1, $xmm2, $xmm3;
|
||||
vaddss $xmm1, $xmm2, [&foo];
|
||||
}
|
||||
}
|
||||
|
||||
/* #expect: test.ll
|
||||
|
||||
"adcxl %ecx, %eax\0Aadcxq %rcx, %rax\0Aaddpd %xmm2, %xmm1\0Aaddps %xmm2, %xmm1\0Aaddsd %xmm2, %xmm1\0Aaddss %xmm2, %xmm1\0Avaddpd %xmm3, %xmm2, %xmm1\0Avaddpd %ymm3, %ymm2, %ymm1\0Avaddpd $0, %xmm2, %xmm1\0Avaddps %xmm3, %xmm2, %xmm1\0Avaddps %ymm3, %ymm2, %ymm1\0Avaddps $0, %xmm2, %xmm1\0Avaddsd %xmm3, %xmm2, %xmm1\0Avaddsd $0, %xmm2, %xmm1\0Avaddss %xmm3, %xmm2, %xmm1\0Avaddss $0, %xmm2, %xmm1\0A", "*m,~{cc},~{rcx},~{xmm1},~{flags},~{dirflag},~{fspr}"
|
||||
Reference in New Issue
Block a user